I’ve worked out the wiring of the SIMM to the CPU board. Unfortunately, the OE signal on the SIMM is hard-wired to ground, which is annoying. I’ll have to lift the legs (pin 16) of each of the RAM chips and hand-wire them together.
This is completely untested…
| Signal | 16500A chip | pin | SIMM signal | SIMM pins | ||
| . | GND | all | 20 | VSS | 1, 39, 72 | |
| . | Vss | all | 10 | VDD | 10, 30, 59 | |
| . | D0 | U43, U52 | 19 | DQ8, DQ24 | 26, 27 | |
| . | D1 | U43, U52 | 18 | DQ7, DQ23 | 24, 25 | |
| . | D2 | U43, U52 | 2 | DQ6, DQ22 | 22, 23 | |
| . | D3 | U43, U52 | 1 | DQ5, DQ21 | 20, 21 | |
| . | D4 | U23, U34 | 2 | DQ4, DQ20 | 8, 9 | |
| . | D5 | U23, U34 | 1 | DQ3, DQ19 | 6, 7 | |
| . | D6 | U23, U34 | 19 | DQ2, DQ18 | 4, 5 | |
| . | D7 | U23, U34 | 18 | DQ1, DQ17 | 2, 3 | |
| . | D8 | U44, U53 | 2 | DQ16, DQ32 | 65, 64 | |
| . | D9 | U44, U53 | 1 | DQ15, DQ31 | 63, 62 | |
| . | D10 | U44, U53 | 18 | DQ14, DQ30 | 61, 60 | |
| . | D11 | U44, U53 | 19 | DQ13, DQ29 | 57, 58 | |
| . | D12 | U24, U35 | 19 | DQ12, DQ28 | 55, 56 | |
| . | D13 | U24, U35 | 18 | DQ11, DQ27 | 53, 54 | |
| . | D14 | U24, U35 | 1 | DQ10, DQ26 | 51, 52 | |
| . | D15 | U24, U35 | 2 | DQ9, DQ25 | 49, 50 | |
| . | W0 | U23, U34, U43, U52 | 3 | nWE | 47 (top half) | |
| . | W1 | U24, U35, U44, U53 | 3 | nWE | 47 (bottom half) | |
| . | RAS | all | 4 | RAS0, RAS2 | 44, 34 | |
| . | CAS0 | U23, U24, U52, U53 | 17 | CAS3, CAS2 | 42, 41 | |
| . | CAS1 | U34, U35, U43, U44 | 17 | CAS1, CAS0 | 43, 40 | |
| . | OE | all | 16 | wire separately | ||
| . | A0 | all | 6 | A0 | 12 | |
| . | A1 | all | 7 | A1 | 13 | |
| . | A2 | all | 8 | A2 | 14 | |
| . | A3 | all | 9 | A3 | 15 | |
| . | A4 | all | 11 | A4 | 16 | |
| . | A5 | all | 12 | A5 | 17 | |
| . | A6 | all | 13 | A6 | 18 | |
| . | A7 | all | 14 | A7 | 28 | |
| . | A8 | all | 15 | A8 | 31 | |
| . | A9 | all | 5 | A9 | 32 |
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