I’ve just been doing some work with the iCE40 series of FPGAs from Lattice Semiconductor. They’re small FPGAs, with up to 7680 gates, and they’re very low-power, which is nice for mobile applications. From what I can gather, Lattice acquired the designs when they bought a company called SiliconBlue in 2011. I’ve been used to using the Lattice Diamond software with their other chips, but the iCE40 chips aren’t supported by Diamond. Instead, they get their own software called iCEcube2. It’s a bit of a pain to use and not very well documented. I’ve just been through the process of starting a project and getting a very basic design working, and I’m writing about it here in case someone else finds it useful.
The iCEcube2 software looks convincingly like an IDE, but it isn’t, really. It doesn’t even seem to have a way of creating new source code files, and the order in which some things have to be done is not at all obvious. I think iCEcube2 is really designed for taking existing designs and implementing them on the Lattice iCE40 chips. While the software is a complete dog’s breakfast, it does have the key advantage of being free. You do need to create a node-locked licence for it using their licencing page.
To start an empty project, double click Project -> New Project. Select the chip you’re going to use. This creates a folder with the title of the project, containing:
- <project>_sbt.project
- <project>_syn.prj
- folder <project>_Implmnt, containing folder sbt, containing folders constraint, log and outputs. All are empty apart from iceCube0.log in log folder.
Now you can add your source files. If you click on ‘Synthesis Tool’, then an ‘Add Synthesis Files’ menu item appears, but clicking on this doesn’t do anything useful. You have to right-click on ‘Add Synthesis Files’ and select ‘Add Files…’ from the pop-up menu. Go figure. I used a very simple VHDL source file:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY test IS PORT ( d: in std_logic; q: out std_logic; qn: out std_logic ); END test; ARCHITECTURE rtl OF test IS BEGIN q <= d; qn <= not d; END rtl;
At this point I’d expect to be able to allocate signal names (d, q and qn, in this case) to pins on the device package. But you can’t do that yet in the wonderful world of iCEcube2. All the buttons on the toolbar are greyed out. The way to proceed is to double click ‘Run Synplify Pro Synthesis’. Hopefully your code will compile without errors, and lots of files get created.
The project folder now contains:
- stdout.log and stdout.log.bak
- synlog.tcl
- loads of stuff under <project>_Implmnt
Two new files appear in the project under ‘P&R Flow’: <project>.edf and <project>.scf.
Now double-click ‘Run P&R’. The design will get placed and routed, and a bitmap gets generated for programming the chip.
At this point the toolbar buttons for timing constraints, pin constraints, floor planner, package view, power estimator and timing analysis become active. Hurrah! Now you can change your pin constraints.
Click on ‘Pin Constraints Editor’, the fourth icon from the left. Put in the pin locations for the signals you want. Make sure you click the ‘locked’ checkboxes on the left hand side, otherwise the place and route process is likely to move them. Press ctrl-S to save. The constraints get saved in <project>_Implmnt\sbt\constraint\<top design file>_pcf_sbt.pcf. You will then get asked to add the file to the project. Say yes.
If you’re using source control, it’s a good idea to add this file to it. I’m not so sure about all the other junk that iCEcube generates.
Now double-click ‘Run P&R’ again and the new bitmap file will be generated, using your pin constraints.
Programming an actual chip (or at least its SPI Flash ROM) needs the Diamond Programming tool, which comes as part of the Lattice Diamond software and *not* as part of iCEcube2. That’s just another couple of gigabytes to download, and another licence (free) to acquire, so it’s a pain, but it does work.
martinjonestechnology 
Hi Martin. I’ve been struggling with the Icecube2 environment for a couple of months now, Have a P2 project (embedded camera vision thingy) on the go for target beta release in May 2016, so it’s gonna soon become a P1 real soon. Finding it difficult to understand the nitty gritty aspects of Lattice’s Place and Route, and trying to tame the global clocks without much luck. Are you still actively working with it?
I’m still working with the chip, yes, though the project I’m working on hasn’t yet pushed the capabilities of the chip we’re using so the standard settings for place and route have worked fine, and the tools identified the clock lines correctly without me having to do anything. It’s going to get more complex shortly, though, so we may well start seeing the same problems!
Hi!
I’ve just started with FPGA programming and this blog was really helpful to get started with iCEcube2!
I was wondering if there is a way to program it without an external programmer. In the tutorial of 2012 there was a programmer button in iCEcube2 but this was removed in 2014 as far as I understood.
Regards
Yes, this is a problem. I don’t know why they removed the programmer button. See Anaon’s reply to this post for how he solved the problem.
Thank you for this tutorial, great work !
It helps me to work with this chip. Allow me to make just one remark, there is no ‘;’ after qn: out std_logic in your entity’s declaration.
Ooh! Thank you, you’re quite right. I’ll remove the erroneous semicolon. I get those wrong all the time anyway – it’s probably my number one VHDL syntax error…
Thanks for this post. Was very helpful in getting me started using iCEcube2 (2016.02.27810) on a iCEblink40-LP1K eval kit.
As an extra comment for others who may find themselves in a similar situation…
The (recommended) Lattice Diamond programming suite requires a Lattice hardware programming tool to talk to the iCEblink40-LP1K eval kit. [I could not get Diamond programming tool to talk to the iCEblink40-LP1K eval kit natively over its USB connection.]
So, to avoid having to buy a Lattice programming tool hardware (expensive, especially compared to the iCEblink40-LP1K eval kit) I instead downloaded iCEcube2 2014.08.26723 from the archive section of the Lattice website. This version includes a separate programming utility that can be used to program the iCEblink40-LP1K eval kit.
I used the latest version of iCECube2 to create the bitmap, and just the programming tool from the 2014 version to program the eval kit.
Hope this helps someone else.
Hello guys,
I’m in the same situation for a couple of weeks now when I must design a project around Lattice ICE40 FPGA and I’ve played a bit with their iCECube2 software. Well, coming from my previous encounter: Xilinx Webpack, iCECube2 is very weird made!
1. First of all I have huge troubles in editing my VHDL codes since integrated editor is worse than Notepad. I’m hardly seeing what I wrote there without any code indent and special word coloring features. To overcome this I decided to use the embedded Synplify Pro synthesis tool but I saw that I simply cannot Place & Route if I won’t close Synplify Pro first. At least, didn’t find any alternatives so far!
2. If you run P&R and you made the mistake of changing few setting in the first place that will make the work for your PC a hard one then you simply cannot cancel the job… There’s no button for that (or I couldn’t see it!). It happened for me that I had to close the iCECube2 from Windows Task Manager.
3. Now I cannot imagine how it will be if I’ll start using Active-HDL simulator since there will be mandatory option for me as I’m not such a good coder to stay out of bugs or weird situations. o, with Active-HDL taken into account there are already three different software environments to work with!
4. …. excluding Diamond Programmer which, I guess, is the single clear, not clumsy software of all listed above! Now are 4 softwares!
There are other issues as well, some I cannot remember now, others are too specific to project and implementations!
The single positive side I could see so far on Lattice is that the FPGA chips are cheap and price/performance ratio is a good one (at least for me)! That was the main reason I pick them for volume applications. Other than that, the IDE is scattered among other software alternatives and is not something packed as I’m used to Xilinx IDEs. I’m assuming Lattice Diamond is close (if not the same as?) Xilinx Webpack? If so then I’ll drop iCE40 and go for MachXO3 or something similar.
Can someone confirm that?
Thank you,
Lucian
Yes, Lattice Diamond is much more similar to Xilinx Webpack. I’ve used it on the Lattice MachXO2 devices and it works well. However, for the ICE devices I tend to use the Xilinx Webpack for code editing and RTL simulation and then just do the synthesis and place and route using iCECube2. That minimises my exposure to iCECube2…
I’d like to point out there is an open source verilog toolchain for ice40… for the 1k and 8k chips alike (but only the LX and HX series). It’s probably better than icecube2 at this point it is however all commandline.
http://www.clifford.at/yosys
Thank you for the comment. Yes, yosys is very cool. I’ve tried using it but ran into problems because the VHDL compiler didn’t understand constants or generics, so I put it to one side. I will definitely be tracking it as the software matures, though.
Chris
Thanks for the guide – the iCECube2 software really does look convincingly like an IDE, but this post made it clear. In the end I selected “Synplify Pro” as my “Synthesis Tool”, then was able to right-click on “Run Synplify Pro”, select Options, and press “Run” to use it as an IDE. Then, when I’m actually done, quite that and run the P&R flow stuff.
I was able to generate VGA on the dev board, great fun!
I’m trying to follow these instructions but struggling with the P&R section. Synthesis works fine, but when I run the placer I get:
I2100: Reading design library: /media/sf_stefandz/Documents/Electronics/Personal/Current_integrator/vhdl/berus-accumulator/vhdl/top_level/top_level_Implmnt/sbt/netlist/oadb-top_level/BFPGA_DESIGN_ep
The master file does not exist
oaInterface::OpenLib_Design OpenDesign failed /media/sf_stefandz/Documents/Electronics/Personal/Current_integrator/vhdl/berus-accumulator/vhdl/top_level/top_level_Implmnt/sbt/netlist/oadb-top_level BFPGA_DESIGN_ep top_level INTERFACE
E2101: Error while reading design library: /media/sf_stefandz/Documents/Electronics/Personal/Current_integrator/vhdl/berus-accumulator/vhdl/top_level/top_level_Implmnt/sbt/netlist/oadb-top_level/BFPGA_DESIGN_ep
E2052: Error while reading inputs for placer
Does anyone know what I am doing wrong here?
Thanks in advance for any pointers 🙂
I don’t know what’s going on there, I’m afraid. It looks like the synthesis hasn’t produced all the files that P&R was expecting, or has put them in a different place. What do you see in the directories it mentions? One thing I would try is recreating the project from scratch using the same source files, to see if there’s something misconfigured in the existing project file.